20/12/2024
【2024-12-11】Mayhwa reports for you
📈According to media reports, TSMC has started 2nm trial production at the Baoshan factory in Hsinchu, with a yield rate of 60%, exceeding TSMC’s internal expectations. In addition to the Baoshan factory, TSMC also plans to launch 2nm trial production at the Kaohsiung factory in the first half of next year.
📈It is understood that foundry mass production of chips requires a yield rate of 70% or higher. According to TSMC's progress, TSMC has time to increase the yield rate to mass production standards before 2nm mass production.
📈With the arrival of the 2nm era, its prices have also risen. It is reported that the price of TSMC's 2nm wafers has exceeded US$30,000. The current price of 3nm wafers is about US$18,500 to US$20,000. By comparison, the price of the 2nm process will be will be greatly improved.
📈It is worth noting that TSMC’s order quotation includes a variety of factors, which are related to specific customers and order volume. Some customers may have some discounts. US$30,000 is a rough figure.
📈Public reports show that since TSMC released the 90nm chip in 2004, the wafer quotation at that time was nearly US$2,000. After the process technology evolved to 10nm in 2016, the quotation increased significantly to US$6,000. After entering the 7nm and 5nm process generations, the quotations exceeded 10,000 US dollars, and 5nm was as high as 16,000 US dollars, and this statistical price has not yet taken into account TSMC's 6% increase in 2023.
📈In October this year, Qualcomm and MediaTek’s flagship chips all switched to the 3nm process, and related terminals set off a wave of price increases. Semiconductor industry insiders predict that due to the high quotations of advanced processes and the high costs of chip manufacturers, the cost pressure will inevitably be passed on To downstream customers or end consumers.
📈It is worth noting that TSMC will use Gate-all-around FETs transistors for the first time at the 2nm process node. In addition, the N2 process can also be paired with NanoFlex technology, providing chip designers with flexible standard components.
📈Compared with the existing N3E process, it is expected that the performance of the N2 process will be improved by 10% to 15% at the same power, or the power consumption will be reduced by 25% to 30% at the same frequency, while the transistor density will be increased by 15%.